The present invention relates to a semiconductor integrated circuit device and particularly to a high-speed low-power semiconductor integrated circuit device having various forms of circuit blocks mounted thereon by mixture.
A list of references in this specification is as follows. The references will be referenced by reference numerals.
[Reference 1]: M. Tsukude et al., 1997 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February 1997, pp.66-67
[Reference 2]: JP-A-8-234851 laid open on Sep. 13, 1966
[Reference 3]: S. Fujii et al., 1986 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February 1986, pp.266-267
[Reference 4]: H. Tanaka et al., IEICE Transaction on Electron, Vol.E75-C, No.11, November 1992, pp.1333-1343
A DRAM circuit operated by a power-supply voltage extVcc in a range of from 1.2 V to 3.3 V supplied from the outside of a chip is described in Reference 1. A word line drive voltage VccP is generated from extVcc by a voltage up-converter VppGen. On the other hand, an array voltage VccA, a peripheral circuit voltage Vpp and a shared-gate level (SGL) are generated from extVcc by respectively correspondingly exclusive voltage down-converters (VCDs).
A semiconductor integrated circuit device having a plurality of modules (circuit blocks) relating to a microcomputer, or the like, is described in Reference 2. Operating power-supply voltages for the plurality of modules are generated as follows. That is, a power-supply voltage Vcc supplied from the outside of a chip is once increased to a boosted voltage VH by a voltage up-converter 4. A plurality of voltage regulators provided so as to correspond to the plurality of modules reduce the boosted voltage VH to generate operating power-supply voltages which are adapted for the plurality of modules respectively and to supply the operating power-supply voltages to the plurality of modules respectively.
A semiconductor integrated circuit device operating with a single power-supply voltage is a subject of each of References 1 and 2. The inventors of the present application has made investigation, prior to the present invention, about a technique for mixing circuits such as DRAM circuits which require various kinds of operating power-supply voltages in a semiconductor integrated circuit supplied with two kinds of power supplies, that is, first power supply VDDQ for I/O circuits (signal input/output) and second power supply VDD for internal logic circuits.
Miniaturization of circuit elements in the inside of an integrated circuit (IC) particularly as represented by size of an MOS transistor has progressed to be adapted to recent improvement in function and speed of the IC owing to improvement in packing density of the IC. Problems against a flow of this technique are increase of power consumption owing to increase of the number of elements and reduction of breakdown voltage owing to the miniaturization of the circuit elements. As a result, reduction of the operating power-supply voltage should be promoted to solve the problems.
The first power supply VDDQ for I/O circuits, however, uses the same voltage for a relatively long term because VDDQ needs to be matched with lots of ICs having specifications determined in the past. Although it is a matter of course that reduction in VDDQ with the times is necessary, the rate of reduction of VDDQ is relatively moderate with respect to years and months. On the other hand, the second power supply VDD for internal logic circuits is free from such limitation of VDDQ, so that reduction of VDD has progressed at a rapid rate.
In order to mix DRAMs in the aforementioned situation, how to supply electric power to the DRAM circuit block is a problem to be solved. That is, the first power supply VDDQ for I/O circuits satisfies the condition of use as a power supply for the DRAM circuit block from the point of view that a relatively high power-supply voltage can be expected to be provided. The first power supply VDDQ, however, has a problem that power-supply noise is large because VDDQ is used for I/O circuits in which a relatively large current flows. That is, when the first power supply VDDQ is used directly for DRAM circuits, there is a fear that VDDQ cannot fulfil its performance sufficiently. On the other hand, it is also to be feared that the voltage of the second power supply VDD may be too low to supply power to the DRAM circuit block in the future because reduction of the voltage is progressing radically. That is, though a word line drive voltage needs the highest voltage in the DRAM circuit block, it is supposed that difficulty occurs in an aspect of power efficiency etc. when a technique which uses a charge pump voltage up-converter for generating the word line drive voltage from VDD is used. The aforementioned problem is not always limited to a chip having logic circuits and DRAMs mixed with the logic circuits. It is supposed that, the aforementioned problem occurs not only in the DRAM circuit block but also in analog circuits such as an AD converter, a DA converter and a PLL; circuits such as a flash memory; or logic circuits such as a microprocessor and a DSP which operate with a super-low voltage of 0.7 V or lower and which are sensitive to the fluctuation of the power-supply voltage.